VHDL多路复用器测试台误差

Question

我是新来的VHDL和试图使测试平台进行多路复用器与5条选线，但它给我的错误（代码是很长，所以我只是复制，其中包括错误的部分）

的代码：

library ieee; 
    use ieee.std_logic_1164.all; 
    use IEEE.std_logic_unsigned.all; 
    use ieee.numeric_std.all; 
    entity Mux_4_to_1_tb is 
    end Mux_4_to_1_tb; 

    architecture tb of Mux_4_to_1_tb is 

    component Mux_4_to_1 is 
     port(clock : in std_logic; 
     D0, D1, D2, D3 : in std_logic; -- the data lines D0=A0 D1=A1 D2=B0 D3=B1 
      S0, S1, S2, S3, S4 : in std_logic; -- the selector switches 
      F : out std_logic_vector(2 downto 0) 
     );-- the output 
    end component; 
    constant clockperiod : time := 20 ns; 
    signal D0, D1, D2, D3, S0, S1 , S2, S3, S4 , F : std_logic; 
    signal selectors : std_logic_vector(4 downto 0); 

    begin 
    mapping: Mux_4_to_1 port map(D0, D1, D2, D3, S0, S1, S2, S3, S4, F); 

    --Concurrent processes 
    process 
    begin 

     S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod; 
     S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '1';wait for clockperiod; 
     S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '1'; S4 <= '0';wait for clockperiod; 
     S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '1'; S4 <= '1';wait for clockperiod; 
     S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '0'; S4 <= '0';wait for clockperiod; 
     S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '0'; S4 <= '1';wait for clockperiod; 
     S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '1'; S4 <= '0';wait for clockperiod; 
     S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '1'; S4 <= '1';wait for clockperiod; 
     S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod; 
     S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '0'; S4 <= '1';wait for clockperiod; 
     S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '1'; S4 <= '0';wait for clockperiod; 
     S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '1'; S4 <= '1';wait for clockperiod; 
     S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '0'; S4 <= '0';wait for clockperiod; 
     S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '0'; S4 <= '1';wait for clockperiod; 
     S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '1'; S4 <= '0';wait for clockperiod; 
     S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '1'; S4 <= '1';wait for clockperiod; 
     S0 <= '1'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod; 
     end process; 

     process(S4, S3, S2, S1, S0) 
     begin 
     selectors <= S0&S1&S2&S3&S4; 
     end process; 

     process 
     begin 

     --The "assert" keyword allows you to test certain 
     --conditions. In other words, the point of assertion is 
     --to allow you to inspect what you expect. 

     --Two test cases are presented here. Feel free 
     --to add your own cases. 

     --TEST 1 
     D0 <= '0'; 
     D1 <= '1'; 
     D2 <= '0'; 
     D3 <= '1'; 
     wait for clockperiod; 
     case selectors is 
     when "00000" => 
      assert(F => "000") report "Error 1: 00000" severity error; 

错误：

** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(70): (vcom-1581) No feasible entries for infix operator '='.
** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(70): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.

错误指向我与断言字线。

而且我得到这个错误的代码结束

代码：

when others => 
    assert true; 
    end case; 
end process; 
end tb; 

错误：

** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(229): VHDL Compiler exiting

错误指向我的最后一行在这里。

Answer 1

您没有提供任何有关该测试平台应该如何操作而不会透露Mux_4_to_1内容的任何见解。

有两个错误的断言语句条件：

assert(F => "000") 

F被声明为类型STD_LOGIC这不是一个数组类型，不能被比作一个字符串值（这将有一个数组类型由上下文确定）。另外，关系运算符应该是>=而不是=>，读作'大于或等于'。 =>是关联中使用的分隔符。

更改关系运算符和改变声明F：

signal D0, D1, D2, D3, S0, S1 , S2, S3, S4 : std_logic; -- , F : std_logic; 
signal F: std_logic_vector (2 downto 0); 

产生错误告诉我们F不能S4关联，告诉我们你有一个参数列表错误。您没有足够的参数。不提供输出关联不是错误，这是之前没有注意到的原因，尽管读者可能会认为您更改了F的声明以先验地排除该错误。

将信号声明时钟：

constant clockperiod : time := 20 ns; 
signal clock: std_logic; 

，并加入一个协会：

begin 
-- mapping: Mux_4_to_1 port map(D0, D1, D2, D3, S0, S1, S2, S3, S4, F); 
mapping: 
    Mux_4_to_1 
     port map (
      clock => clock, 
      D0 => D0, 
      D1 => D1, 
      D2 => D2, 
      D3 => D3, 
      S0 => S0, 
      S1 => S1, 
      S2 => S2, 
      S3 => S3, 
      S4 => S4, 
      F => F 
     ); 

允许您的代码分析（通过与他人的选择找到的代码串联到年底VHDL代码，您不提供Minimal, Complete and Verifiable example）。

注：

1. clock没有显示驱动的变化说明，必要时为您的测试应该由测试平台进行驱动。
2. Mux_4_to_1的临时端口映射中显示正式关联，它允许您查看对实际端口关联缺少或错误的形式。
3. 多余的括号可能会掩盖错误。如果他们所包含的表达在没有他们的情况下是合法的，他们只是合法的它可以更改您看到的错误消息。缺乏适当的关系运算符会导致语法错误。