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我是vhdl的新手，我一直在为d-flipflop和一个缓冲区编写测试平台，它允许我在测试仪上根据缓冲区写入我的dflipflop输出，但我无法更改测试台中的输入值可以帮助我。这是我的VHDL和测试平台为它的代码..用于dflipflop的VHDL测试平台
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Dflipflop1 is
port
(D0_in,EN_low,in4 :in std_logic;
q :out std_logic
);
end entity Dflipflop1;
architecture Dff of Dflipflop1 is
begin
process(D0_in,EN_low,in4)
begin
if (in4 = '1' and EN_low = '0') then
q <= D0_in;
else
q <= '0';
end if ;
end process;
end architecture Dff;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tribuffer1 is
port
(in1_b,in2_b :in std_logic;
out_b :out std_logic
);
end entity tribuffer1;
architecture tbf of tribuffer1 is
begin
process(in1_b,in2_b)
begin
if (in1_b = '0') then
out_b <= in2_b;
else
out_b <= 'Z';
end if ;
end process;
end architecture tbf;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pin11 is
port
(
RD,RESET,EN_low,WR,CS5A,CS6A,CS7A,D7_in,D6_in,D5_in,D4_in,D3_in,D2_in,D1_in,D0_in: in std_logic;
D0_out,D1_out,D2_out,D3_out,D4_out,D5_out,D6_out,D7_out: out std_logic
--P0,P1,P2,P3,P4,P5: out std_logic_vector (7 downto 0)
);
end entity pin11;
architecture logic of pin11 is
component Dflipflop1 is
port
(D0_in,EN_low,in4 :in std_logic;
q :out std_logic
);
end component;
component tribuffer1 is
port
(in1_b,in2_b : in std_logic;
out_b :out std_logic
);
end component;
signal Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15,Q16,Q17,Q18 : std_logic;
begin
D1 : Dflipflop1 port map(RD,EN_low,'1',Q1);
D2 : Dflipflop1 port map(WR,En_low,'1',Q4);
-----D0 pin------------
D0_R : Dflipflop1 port map(D0_in,EN_low,RESET,Q2);
B0_R : tribuffer1 port map(Q1,Q2,D0_out);
---- D1 pin--------
D1_R : Dflipflop1 port map(D1_in,EN_low,RESET,Q5);
B1_R : tribuffer1 port map(Q1,Q5,D1_out);
---- D2 pin--------
D2_R : Dflipflop1 port map(D2_in,EN_low,RESET,Q7);
B2_R : tribuffer1 port map(Q1,Q7,D2_out);
---- D3 pin--------
D3_R : Dflipflop1 port map(D3_in,EN_low,RESET,Q9);
B3_R : tribuffer1 port map(Q1,Q9,D3_out);
---- D4 pin--------
D4_R : Dflipflop1 port map (D4_in,EN_low,RESET,Q11);
B4_R : tribuffer1 port map(Q1,Q11,D4_out);
---- D5 pin--------
D5_R : Dflipflop1 port map(D5_in,EN_low,RESET,Q13);
B5_R : tribuffer1 port map(Q1,Q13,D5_out);
---- D6 pin--------
D6_R : Dflipflop1 port map(D6_in,EN_low,RESET,Q15);
B6_R : tribuffer1 port map(Q1,Q15,D6_out);
---- D7 pin--------
D7_R : Dflipflop1 port map(D7_in,EN_low,RESET,Q17);
B7_R : tribuffer1 port map(Q1,Q17,D7_out);
end architecture logic;
architecture logic of pin11 is
component Dflipflop1 is
port
(D0_in,EN_low,in4 :in std_logic;
q :out std_logic
);
end component;
component tribuffer1 is
port
(in1_b,in2_b : in std_logic;
out_b :out std_logic
);
end component;
signal Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15,Q16,Q17,Q18 : std_logic;
begin
D1 : Dflipflop1 port map(RD,EN_low,'1',Q1);
D2 : Dflipflop1 port map(WR,En_low,'1',Q4);
-----D0 pin------------
D0_R : Dflipflop1 port map(D0_in,EN_low,RESET,Q2);
B0_R : tribuffer1 port map(Q1,Q2,D0_out);
---- D1 pin--------
D1_R : Dflipflop1 port map(D1_in,EN_low,RESET,Q5);
B1_R : tribuffer1 port map(Q1,Q5,D1_out);
---- D2 pin--------
D2_R : Dflipflop1 port map(D2_in,EN_low,RESET,Q7);
B2_R : tribuffer1 port map(Q1,Q7,D2_out);
---- D3 pin--------
D3_R : Dflipflop1 port map(D3_in,EN_low,RESET,Q9);
B3_R : tribuffer1 port map(Q1,Q9,D3_out);
---- D4 pin--------
D4_R : Dflipflop1 port map (D4_in,EN_low,RESET,Q11);
B4_R : tribuffer1 port map(Q1,Q11,D4_out);
---- D5 pin--------
D5_R : Dflipflop1 port map(D5_in,EN_low,RESET,Q13);
B5_R : tribuffer1 port map(Q1,Q13,D5_out);
---- D6 pin--------
D6_R : Dflipflop1 port map(D6_in,EN_low,RESET,Q15);
B6_R : tribuffer1 port map(Q1,Q15,D6_out);
---- D7 pin--------
D7_R : Dflipflop1 port map(D7_in,EN_low,RESET,Q17);
B7_R : tribuffer1 port map(Q1,Q17,D7_out);
end architecture logic;
这是测试平台
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--- entity declaration for your testbench.
ENTITY test_bench1 IS
END test_bench1;
ARCHITECTURE logic OF test_bench1 IS
-- Component Declaration for the Unit Under Test (UUT)
component pin11 --'test' is the name of the module needed to be tested.
--just copy and paste the input and output ports of your module as such.
port
(
RD,RESET,EN_low,WR,CS5A,CS6A,CS7A,D7_in,D6_in,D5_in,D4_in,D3_in,D2_in,D1_in,D0_in: in std_logic;
D0_out,D1_out,D2_out,D3_out,D4_out,D5_out,D6_out,D7_out: out std_logic
--P0,P1,P2,P3,P4,P5: out std_logic_vector (7 downto 0)
);
end component;
signal RD,RESET,EN_low,WR,CS5A,CS6A,CS7A,D7_in,D6_in,D5_in,D4_in,D3_in,D2_in,D1_in,D0_in,D0_out,D1_out,D2_out,D3_out,D4_out,D5_out,D6_out,D7_out: std_logic;
-- signal P0,P1,P2,P3,P4,P5: std_logic_vector(7 downto 0);
begin
mapping : pin11 port map(RD,RESET,EN_low,WR,CS5A,CS6A,CS7A,D7_in,D6_in,D5_in,D4_in,D3_in,D2_in,D1_in,D0_in,D0_out,D1_out,D2_out,D3_out,D4_out,D5_out,D6_out,D7_out);--,P0,P1,P2,P3,P4,P5);
test:process
variable errCnt : integer := 0;
begin
CS5A <= '0';
CS6A <= '0';
CS7A <= '0';
RD <= '0';
RESET <= '1';
EN_low <= '0';
--CLK <= '0';
WR <= '1';
D0_in <= '0';
D1_in <= '1';
D2_in <= '1';
D3_in <= '0';
D4_in <= '1';
D5_in <= '0';
D6_in <= '1';
D7_in <= '0';
wait for 5 ns;
assert(D1_out = '1') report "Cout error 3" severity error;
if(D0_out /= '1') then
errCnt := errCnt + 1;
end if;
D4_in <= '0';
D5_in <= '1';
D6_in <= '0';
D7_in <= '1';
if(errCnt = 0) then
assert false report "Success!" severity note;
else
assert false report "Failure!" severity note;
end if;
wait;
end process;
end logic;
我的输入值始终为01010110（D7_in到D0_in）