SR Fliflop的VHDL测试平台

Question

我想用VHDL实现SR触发器。我编写了触发器的代码以及测试平台。但测试平台不能正确编译，并给出我无法弄清楚的错误。我正在使用ghdl进行编译。请帮忙。

这是触发器的代码。

library ieee; 
use ieee.std_logic_1164.all; 

entity sr_flipflop is 
    port 
    (
     s,r,clock: in std_logic; 
     q,qbar: inout std_logic 
    ); 
end sr_flipflop; 

architecture arc of sr_flipflop is 
    signal x,y: std_logic; 
begin 
    process (clock,s,r) begin 
     x<=r and clock; 
     y<=s and clock; 
     q<=qbar nor x after 10 ns; 
     qbar<=q nor y after 10 ns; 
    end process; 
    process (x,y) begin 
     q<=qbar nor x after 5 ns; 
     qbar<=q nor y after 5 ns; 
    end process; 
end architecture arc; 

这是测试平台的代码。

library ieee; 
use ieee.std_logic_1164.all; 

entity sr_flipflop_tb is 
end entity sr_flipflop_tb; 

architecture arc of sr_flipflop is 
    component sr_flipflop is 
     port 
     (
      s,r,clock: in std_logic; 
      q,qbar: inout std_logic 
     ); 
    end component sr_flipflop; 

    signal clock:std_logic:='0'; 
    signal s,r:std_logic; 
    signal q:std_logic:='0'; 
    signal qbar:std_logic:='1'; 
    constant half_period:time:=30 ns; 

begin 
    port_map:sr_flipflop port map(clock=>clock,s=>s,r=>r,q=>q,qbar=>qbar); 

    process begin 
     clock <= not clock after half_period; 
    end process; 
    process begin 
     s<='0'; 
     r<='0'; 

     s<='0' after 40 ns; 
     r<='1' after 40 ns; 

     s<='1' after 80 ns; 
     r<='0' after 80 ns; 

     s<='1' after 120 ns; 
     r<='1' after 120 ns; 
    end process; 

end architecture arc; 

的第一个文件编译没有错误，但是当我给在CMD下面的命令，

ghdl -a sr_flipflop_tb.vhd 

我收到以下错误：

sr_flipflop_tb.vhd:16:15: identifier 'clock' already used for a declaration 
sr_flipflop.vhd:7:20: previous declaration: port "clock" 
sr_flipflop_tb.vhd:17:15: identifier 's' already used for a declaration 
sr_flipflop.vhd:7:16: previous declaration: port "s" 
sr_flipflop_tb.vhd:17:17: identifier 'r' already used for a declaration 
sr_flipflop.vhd:7:18: previous declaration: port "r" 
sr_flipflop_tb.vhd:18:15: identifier 'q' already used for a declaration 
sr_flipflop.vhd:8:16: previous declaration: port "q" 
sr_flipflop_tb.vhd:19:15: identifier 'qbar' already used for a declaration 
sr_flipflop.vhd:8:18: previous declaration: port "qbar" 
sr_flipflop_tb.vhd:26:16: port "clock" can't be assigned 
sr_flipflop_tb.vhd:29:16: port "s" can't be assigned 
sr_flipflop_tb.vhd:30:16: port "r" can't be assigned 
sr_flipflop_tb.vhd:32:16: port "s" can't be assigned 
sr_flipflop_tb.vhd:33:16: port "r" can't be assigned 
sr_flipflop_tb.vhd:35:16: port "s" can't be assigned 
sr_flipflop_tb.vhd:36:16: port "r" can't be assigned 
sr_flipflop_tb.vhd:38:16: port "s" can't be assigned 
sr_flipflop_tb.vhd:39:16: port "r" can't be assigned 

请一些启发。谢谢。在您的测试平台

Answer 1

7号线是

architecture arc of sr_flipflop is 

这似乎是一个复制粘贴&错误，应该是

architecture arc of sr_flipflop_tb is 

这应当引起这些错误消息。

请注意，您的代码本身并不完美。在Modelsim中，你的测试平台根本不能运行（我不知道GHDL）。也许退房this tutorial。它有点过时了，但它工作。

Answer 2

这

entity sr_flipflop_tb is 
end entity sr_flipflop_tb; 

architecture arc of sr_flipflop is 

应该是这个

entity sr_flipflop_tb is 
end entity sr_flipflop_tb; 

architecture arc of sr_flipflop_tb is 
        ^^^^^^^^^^^^^^ 

Answer 3

不回答你的问题，但是

process (clock,s,r) begin 
    x<=r and clock; 
    y<=s and clock; 
    q<=qbar nor x after 10 ns; 
    qbar<=q nor y after 10 ns; 
end process; 
process (x,y) begin 
    q<=qbar nor x after 5 ns; 
    qbar<=q nor y after 5 ns; 
end process; 

你有两个进程驾驶q和q_bar。这不会按预期工作。由于多个驱动程序，信号将解析为'X'。

---

下一个问题是敏感列表。

process (x,y) begin 
    q<=qbar nor x after 5 ns; 
    qbar<=q nor y after 5 ns; 
end process; 

q和q_bar不在灵敏度列表上。因此，q和q_bar将不会更新，如果任一q_bar， q已更新。

---

下一个问题是信号更新。

信号将不会更新，直到下一个增量周期。过程完成后会发生增量循环。所以：

process (clock,s,r) begin 
    x<=r and clock; 
    q<=qbar nor x after 10 ns; 
end process; 

在x由于r或clock变化的变化将不会在此下一行适用于q，因为x不会直到下一个增量周期进行更新。

---

最后，不要使用inout端口类型。

如果您想内部访问输出端口，可以使用VHDL-2008进行编译，也可以使用中间信号。

architecture ... of ... 
    signal q_int : std_logic; 
begin 
    [... assign and use q_int] 
    q <= q_int; 
end architecture; 

但最好开始使用VHDL-2008