module stimulus;
reg [511:0]FROM_LS;
reg CLOCK;
reg [2:0]HMIC_CTRL;
reg [20:0]BRANCH_CTRL;
reg [63:0]TO_IF_ID;
reg FLUSH_CTRL;
reg [20:0]TO_LS;
inst_line_buf ILB(FLUSH_CTRL,TO_LS,FROM_LS,CLOCK,HMIC_CTRL,BRANCH_CTRL,TO_IF_ID);
// setup clock
initial
begin
#10 CLOCK = ~CLOCK;
// apply stimulus
FROM_LS[511:480]= 32'b00011_00000_00100_01100_11100_10111_01;
FROM_LS[479:448]=32'b000_11000_00100_01111_11111_00011_1000;
HMIC_CTRL[2:0]=3'b000;
BRANCH_CTRL[20:0]=20'b00000_00000_00000_00000;
#2 $display("FLUSH CONTROL=%b, TO_LS= %b",FLUSH_CTRL,TO_LS);
end
endmoduleVerilog测试模拟误差
,我发现了以下错误:
# Loading work.inst_line_buf
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (512 or 512) does not match connection size (1) for port 'from_LS'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(1).
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (21) for port 'clk'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(2).
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (3 or 3) does not match connection size (512) for port 'hmic_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(3).
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (21 or 21) does not match connection size (1) for port 'branch_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(4).
# Region: /stimulus/ILB
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'to_if_id'".
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (64 or 64) does not match connection size (3) for port 'to_if_id'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(5).
# Region: /stimulus/ILB
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'flush_ctrl'".
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (21) for port 'flush_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(6).
# Region: /stimulus/ILB
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'to_LS'".
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (21 or 21) does not match connection size (64) for port 'to_LS'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(7).
# Region: /stimulus/ILB
# Error loading design
至少说明我们的警告信息! – Marty 2011-04-07 22:53:57
@marty:我已经包含了testbench的代码,并且还包含错误。你能帮我解决这个问题吗? – kinirashmi 2011-04-09 15:10:10