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我已经写了一个64位乘法器的代码使用四部分分裂技术。使用的设备是顶点6.该代码包含4个16 * 16乘法器和6个17 * 17个带符号的乘法器。共10个乘法器。但合成后的总结告诉我已经使用了16个DSP片，我必须将其限制为10.任何人都可以请帮助我展示如何减少此处使用的DSP片的数量。以下是我的代码。64位乘法器在Fpga
'module mul64(a,b,clk,c);
input [63:0] a,b;
input clk;
output reg [127:0] c;
wire [31:0] pp0,pp1,pp2,pp3;
reg signed [16:0] a32,b32,a31,b31,a30,b30,a21,b21,a20,b20,a10,b10;
reg signed [33:0] p32,p31,p30,p21,p20,p10;
reg [33:0] s1,s2,s4,s5;
reg [33:0] s3;
reg [49:0] ppr1;
reg [65:0] ppr2;
reg [81:0] ppr3;
reg [97:0] ppr4;
reg [113:0] ppr5;
reg [127:0] ppr6;
// 16*16 multipliers
mul16 a1 (a[15:0],b[15:0],clk,pp0);
mul16 a2 (a[31:16],b[31:16],clk,pp1);
mul16 a3 (a[47:32],b[47:32],clk,pp2);
mul16 a4 (a[63:48],b[63:48],clk,pp3);
always @ (posedge clk)
begin
a32 <= a[63:48]-a[47:32];
b32 <= b[63:48]-b[47:32];
a31 <= a[63:48]-a[31:16];
b31 <= b[63:48]-b[31:16];
a30 <= a[63:48]-a[15:0];
b30 <= b[63:48]-b[15:0];
a21 <= a[47:32]-a[31:16];
b21 <= b[47:32]-b[31:16];
a20 <= a[47:32]-a[15:0];
b20 <= b[47:32]-b[15:0];
a10 <= a[31:16]-a[15:0];
b10 <= b[31:16]-b[15:0];
// 17*17 signed multipliers
p32 <= a32*b32;
p31 <= a31*b31;
p30 <= a30*b30;
p21 <= a21*b21;
p20 <= a20*b20;
p10 <= a10*b10;
// partial products according to 4 parts splitting technique
s1 <= pp1+pp0-p10;
s2 <= pp2+pp1+pp0-p20;
s3 <= pp3+pp0-p30+pp2+pp1-p21;
s4 <= pp3+pp2+pp1-p31;
s5 <= pp3+pp2-p32;
// shifting of the partial products
ppr1 <= {s1,16'b0};
ppr2 <= {s2,32'b0};
ppr3 <= {s3,48'b0};
ppr4 <= {s4,64'b0};
ppr5 <= {s5,80'b0};
ppr6 <= {pp3,96'b0};
// sum of partial products
c <= pp0+ppr1+ppr2+ppr3+ppr4+ppr5+ppr6;
end
endmodule'