Baysis2 Verilog - 7段显示的第一位不能工作

我正试图在我的baysis2 FGPA上使用verilog创建一个简单的4位密码系统。我想使用7段显示器显示输入的数字（它们将使用键盘输入）。现在我只是测试以确保输入正确的数字。问题是，七段显示器的第一个数字在所有其他显示器都没有亮时不亮。我已经在多个电路板上尝试过，并且所有其他数字都是由相同的电线启用的，都很好。这是为什么发生？Baysis2 Verilog - 7段显示的第一位不能工作

module enter_password(
    input wire clk, reset, 
    input wire ps2d, ps2c, rx_en, 
    output wire [6:0] seven_seg_display, 
    output wire assert_seg); 

    wire [7:0] scan_out; 
    wire [7:0] ascii_code; 

    //initial seven_seg_display = 7'b0000000; 

    assign assert_seg = 1'b1; 

    // instantiate ps2 receiver 
    ps2_rx ps2_rx_unit(
     .clk(clk), .reset(reset), .rx_en(1'b1), 
     .ps2d(ps2d), .ps2c(ps2c), 
     .rx_done_tick(scan_done_tick), .dout(scan_out)); 

    // instantiate key-to-ascii code conversion circuit 
    Scan_to_ascii key2ascii(.key_code(scan_out), .ascii_code(ascii_code)); 

    assign seven_seg_display = 
     ascii_code == 8'h30 ? 7'b0000001: //0 
     ascii_code == 8'h31 ? 7'b1001111: //1 
     ascii_code == 8'h32 ? 7'b0010010: //2 
     ascii_code == 8'h33 ? 7'b0000110: //3 
     ascii_code == 8'h34 ? 7'b1001100: //4 
     ascii_code == 8'h35 ? 7'b0100100: //5 
     ascii_code == 8'h36 ? 7'b0100000: //6 
     ascii_code == 8'h37 ? 7'b0001111: //7 
     ascii_code == 8'h38 ? 7'b0000000: //8 
     ascii_code == 8'h39 ? 7'b0000100: //9 
          7'b1111111; //e for error 0 
endmodule

UCF

NET "seven_seg_display[6]" LOC = "L14"; # Bank = 1, Signal name = CA 
NET "seven_seg_display[5]" LOC = "H12"; # Bank = 1, Signal name = CB 
NET "seven_seg_display[4]" LOC = "N14"; # Bank = 1, Signal name = CC 
NET "seven_seg_display[3]" LOC = "N11"; # Bank = 2, Signal name = CD 
NET "seven_seg_display[2]" LOC = "P12"; # Bank = 2, Signal name = CE 
NET "seven_seg_display[1]" LOC = "L13"; # Bank = 1, Signal name = CF 
NET "seven_seg_display[0]" LOC = "M12"; # Bank = 1, Signal name = CG 
#NET "dp" LOC = "N13"; # Bank = 1, Signal name = DP 

NET "assert_seg" LOC = "K14"; # Bank = 1, Signal name = AN3 
NET "assert_seg" LOC = "M13"; # Bank = 1, Signal name = AN2 
NET "assert_seg" LOC = "J12"; # Bank = 1, Signal name = AN1 
NET "assert_seg" LOC = "F12"; # Bank = 1, Signal name = AN0

来源

2015-11-26 Noah Mendoza

为什么'assert_seg'分配给4个引脚？该代码不应该通过“翻译”步骤。您的代码没有7段显示器的时间复用器，需要驱动所有4位数字。请参阅电路板的原理图以进行说明。 – Paebbels

电路板的原理图在哪里？ – e19293001

您是否尝试断言最低位？也就是说，'wire assert_seg [3：0]'''assert_seg = 4'b0001' - 'NET'assert_seg [0]“LOC =”K14“'。该电路被设计为在任何时间只运行7段显示器中的一个（其更新频率高于人眼可以感知的）。也许它不能在所有显示器上持续显示一个值。 [来源]（http://www.digilentinc.com/Data/Products/BASYS2/Basys2_rm.pdf） – Hida

的问题是，七段显示的第一个数字不亮时，所有其他的人做。

我假设有你的七段显示两位数字，所以你需要有14-bit seven_seg_display输出从enter_password模块

变化

output wire [6:0] seven_seg_display,

到

output wire [13:0] seven_seg_display,

您还可能需要更改以下代码的逻辑以支持a 14-bit seven_seg_display和多路复用器以确定哪些的seven_seg_display一半将是ascii_code分配：

assign seven_seg_display = 
     ascii_code == 8'h30 ? 7'b0000001: //0 
     ascii_code == 8'h31 ? 7'b1001111: //1 
     ascii_code == 8'h32 ? 7'b0010010: //2 
     ascii_code == 8'h33 ? 7'b0000110: //3 
     ascii_code == 8'h34 ? 7'b1001100: //4 
     ascii_code == 8'h35 ? 7'b0100100: //5 
     ascii_code == 8'h36 ? 7'b0100000: //6 
     ascii_code == 8'h37 ? 7'b0001111: //7 
     ascii_code == 8'h38 ? 7'b0000000: //8 
     ascii_code == 8'h39 ? 7'b0000100: //9 
          7'b1111111; //e for error 0

来源

2015-11-26 02:51:09 e19293001

Baysis2 Verilog - 7段显示的第一位不能工作

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