7段MUX不显示想要的数字.- Verilog

Question

我想在7段显示器上显示范围从0.0到99.5，步长0.5的数字。 我有3个七段显示器可用，它们连接在一个多路复用器中，所以我有7个针段和3个选择针脚的选择位。 在附上的Verilog代码中，我显示了特定的数字，问题是我不知道如何使 成为一个循环，它将设置特定数字的选择引脚。 有人可以帮我轻松实现吗？ 当前的代码只显示零。 我注意到，选择引脚设置和选择寄存器移位，但数字不变。 它总是显示我希望显示的顺序中的最后一位数字。

module LED_7seg(
    input clk, 
    output segA, segB, segC, segD, segE, segF, segG, segDP, 
    output dig0, dig1, dig2 

); 

// cnt is used as a prescaler - fbrd/prescaler 
reg [23:0] cnt; 
always @(posedge clk) cnt <= cnt+24'h1; 
wire cntovf = &cnt; 

// BCD is a counter that counts from 0 to 9 
reg [3 : 0] BCD; 
wire [15 : 0] BCD16; 

// set of number 
assign BCD16 = 'h350; 



reg [2 : 0] Digit; 
always @(posedge clk) 
begin 
     if(Digit == 3'h4) begin 
      Digit <= 3'h1; 
     end else begin 
      Digit <= Digit + 3'h2; 
     end 
     case(Digit) 
     3'h1:   BCD = BCD16[3 : 0]; 
     3'h2:   BCD = BCD16[7 : 4]; 
     3'h4:   BCD = BCD16[11 : 8]; 
     default: BCD = BCD16[3 : 0]; 
     endcase 
end 


reg [7:0] SevenSeg; 
always @(*) 
case(BCD) 
    4'h0: SevenSeg = 8'b11111100; 
    4'h1: SevenSeg = 8'b01100000; 
    4'h2: SevenSeg = 8'b11011010; 
    4'h3: SevenSeg = 8'b11110010; 
    4'h4: SevenSeg = 8'b01100110; 
    4'h5: SevenSeg = 8'b10110110; 
    4'h6: SevenSeg = 8'b10111110; 
    4'h7: SevenSeg = 8'b11100000; 
    4'h8: SevenSeg = 8'b11111110; 
    4'h9: SevenSeg = 8'b11110110; 
    default: SevenSeg = 8'b00000000; 
endcase 

assign {dig0, dig1, dig2} = Digit; 
assign {segA, segB, segC, segD, segE, segF, segG, segDP} = ~SevenSeg; 


endmodule 

Answer 1

我与选择数字模式问题，数字之间切换太快。这是一个corecct代码：

/* Author: Grega Mocnik 
    Description: 7 segment driver for 3 digits display. 
    Date: 3.3.2017 
    Version: V1 
    ***************************************************** 
*/ 
module LED_7seg(
    input clk, 
    output segA, segB, segC, segD, segE, segF, segG, segDP, 
    output dig0, dig1, dig2 
); 
// Prescaler of board frequency 
// For normall view on 7 segment displey must be switch frequency betwen 
// segments more than 100 Hz. - At 100Hz, a display cycle would last 10ms 
// (and each display would be lit 3.33ms per cycle). 
// cnt is used as a prescaler - 
// equation: frekvneca_zeljena = (fboard)/(2 * (1 + Presclaer)) 
reg [18:0] cnt; 
always @(posedge clk) cnt <= cnt+19'h1; 
wire cntovf = &cnt; 

// Declare of BCD register, for select segment and digit's 
reg [3 : 0] BCD; 
wire [15 : 0] BCD16; 

// Set of number - for number set this register first two numbers 
// is before point. example: 'h351 = 35.1 
assign BCD16 = 'h846; 

// Declare of SevenSeg register - select segment 
reg [7:0] SevenSeg; 
// Declare of Digit register - select digit 
reg [2 : 0] Digit; 

// Switch between digits 
// Switch pattern is 1 2 4 1 2 4 ... 
// because, 1 in binary 001 and 2 in binary 010 and 4 in binary 100 ... 
// have common anode and then select digit with 1 and select segment with 0. 
always @(posedge clk) 
begin 
    if(cntovf) begin 
     Digit <= Digit * 3'h2; 
     if(Digit > 3'h4) begin Digit <= 3'h1;end 
     if(Digit == 3'h0) begin Digit <= 3'h1;end 
    end 
end 
// Select each number from BCD16 reg. 
// All number to 10 we can show with 4 bit's in binry world. 
// Now we can see for example number 351 binary pattern 0011 0101 0001 - 
// - first 4 bit's for first digit in number 
// - second 4 bit's for second digit in number 
// - third 4 bit's for third digit in number 
always @(*) 
     case(Digit) 
     3'h1:  BCD = BCD16[3 : 0]; 
     3'h2:  BCD = BCD16[7 : 4]; 
     3'h4:  BCD = BCD16[11 : 8]; 
     default: BCD = BCD16[3 : 0]; 
     endcase 

assign {dig0, dig1, dig2} = Digit; 

// Explain pattern is write for common cathode. 
// The last bit is for dot segment. 
always @(*) 
case(BCD) 
    4'h0: SevenSeg = 8'b11111101; 
    4'h1: SevenSeg = 8'b01100001; 
    4'h2: SevenSeg = 8'b11011011; 
    4'h3: SevenSeg = 8'b11110011; 
    4'h4: SevenSeg = 8'b01100111; 
    4'h5: SevenSeg = 8'b10110111; 
    4'h6: SevenSeg = 8'b10111111; 
    4'h7: SevenSeg = 8'b11100001; 
    4'h8: SevenSeg = 8'b11111111; 
    4'h9: SevenSeg = 8'b11110111; 
    //default: SevenSeg = 8'b00000000; 
endcase 

// Assign output segment, - output is invert because we have common anonde display 
// segment binary pattern is write for common cathode display 
assign {segA, segB, segC, segD, segE, segF, segG, segDP} = ~SevenSeg; 

endmodule