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我遇到一个更多的困难，同时将fifo代码实例化到我的顶级模块。我想从我的串行端口（接收子系统）存储一些数据集，例如“欢迎来到FPGA的世界”，然后我想要找回它说按下fpga板上的按钮或FIFO已满时。我写了我的fifo代码和串行通信代码。想法是从键盘 - >接收子系统 - > FIFO - >传输子系统 - >超级终端发送的数据。目前我正在使用8位宽的fifo，并说28深，只是为了存储一些小数据。请在这方面帮助我，我该如何实现它。我有来自保存在register_save中的接收器的字节。 fifo codeFIFO实现 - VHDL
inst_bit8_recieve_unit : entity work.byte_recieve_8N1
port map (ck => ck,
reset => reset,
new_byte_in_buffer => new_byte_in_buffer,
byte_read_from_buffer => byte_read_from_buffer,
recieve_buffer => register_save,
JA_2 => JA(2));
---------------------FIFO instantiate-------------------------------
inst_of_fifo_Recieve_unit : entity work.fifo
generic map (B => data_bits, W => fifo_width)
port map (ck => ck,
reset => reset,
rd => rd_rx,
wr => wr_rx,
write_data => num_recieved,
read_data => num_recieved_fifo,
empty => empty_rx,
full => full_rx);
inst_bit8_transmit_unit : entity work.byte_transmit_8N1
port map (ck => ck,
reset => reset,
send_byte_ready => send_byte_ready,
send_byte_done => send_byte_done ,
send_buffer => num_send,
JAOUT_0 => JAOUT);
proc_send5byte: process(ck, reset, state_byte5, send_byte_done, num_send, state_button_0, num_recieved_fifo, rd_rx)
begin
if reset = '1' THEN
state_byte5 <= idle;
send_byte_ready <='0';
num_send <= "00000000" ;
else
if rising_edge(ck) then
case state_byte5 is
when idle => ---- in this, if btn(0) is high i.e pressed then only state_byte5 will go to next state
if state_button_0 = transit_pressed then
state_byte5 <= byte;
end if;
-----===============================================================
when byte =>
if (not empty_rx = '1') then
if send_byte_ready ='0' and send_byte_done = '0' then ----here if condition is satified the send_byte_ready will be set
send_byte_ready <='1'; --------- shows next byte is ready
num_send <= num_recieved_fifo;
rd_rx <='1';
end if;
end if;
if send_byte_ready = '1' and send_byte_done = '1' then --- during load state send_byte will be resets
send_byte_ready <='0';
rd_rx <= '0';
state_byte5 <= idle; ----------- go back to idle
end if;
--end if;
---===============================================================
when others =>
state_byte5 <= idle; ------------- for other cases state state _byte5 will be in idle
send_byte_ready <= '0';
rd_rx <= '0';
end case;
end if;
end if;
end process;
proc_recieving_byte : process (ck, reset, register_save, new_byte_in_buffer, full_rx, num_recieved, wr_rx)
begin
if reset = '1' then
byte_read_from_buffer <= '0';
else
if rising_edge(ck) then
if full_rx = '0' then
if new_byte_in_buffer = '1' and byte_read_from_buffer = '0' then
byte_read_from_buffer <= '1';
wr_rx <= '1';
num_recieved(7 downto 0) <= register_save(7 downto 0);
end if;
end if;
if new_byte_in_buffer = '0' then
byte_read_from_buffer <= '0';
wr_rx <= '0';
end if;
--end if;
end if;
end if;
end process;
现在只是补充更正后的代码，这似乎是工作。问题araises增加fifo的深度时。当深度> 2时，则每三个字节都丢失。 请帮忙，为什么我丢失数据。
如果您有关于某些特定代码的具体问题，请询问并且有人会很乐意回答。但这不是一个代码写入服务。 –
嗨。我理解你的话。但我需要帮助增加或追加收到的字节，直到fifo充满。这一部分让我感到困惑，我是否应该每次检查FIFO的深度，同时保存字节，否则它会自行保存，直到它已满。 – skale
这个问题完全不可理解。请阅读[我如何问一个好问题]（https://stackoverflow.com/help/how-to-ask）。 – JHBonarius