Xilinx的“Dead code”

我正在写一些VHDL代码。但是，综合工具将cell3，cell2和cell1标识为“已死”代码，并且不会对其进行合成。Xilinx的“Dead code”

我真的不知道是怎么回事导致细胞3,2,1在合成中被删除;我已经审查了5次以上，并问了几个不同的人，我找不到“为什么”。

不寻找解决方案，只是一个指向为什么。

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 



entity multiply is 
    Port (a : in STD_LOGIC_VECTOR (3 downto 0); 
      b : in STD_LOGIC; 
      clk : in STD_LOGIC; 
      rst : in STD_LOGIC; 

      p : out STD_LOGIC); 

end multiply; 

architecture Behavioral of multiply is 

    component cell_a port(
       s: in std_logic; 
       c: in std_logic; 
       a: in std_logic; 
       b: in std_logic; 
       clk: in std_logic; 

       c_out: out std_logic; 
       s_out: out std_logic); 
    end component; 

    signal c_s_0: std_logic; --loopback wire for cell 0 from carry to sum 
    signal c_s_1: std_logic; 
    signal c_s_2: std_logic; 
    signal c_s_3: std_logic; 

    signal xfer1_0: std_logic; --wire between 1 and 0 
    signal xfer2_1: std_logic; --"  2 and 1 
    signal xfer3_2: std_logic;  --"  3 and 2 


begin 

    cell3: cell_a port map(
            clk => clk, 
            s => c_s_3 , c => '0', a => a(3), b => b, 
            c_out => c_s_3, s_out => xfer3_2 
            ); 

    cell2: cell_a port map(
            clk => clk, 
            s => c_s_2 , c => xfer3_2, a => a(2), b => b, 
            c_out => c_s_2, s_out => xfer2_1 
            ); 

    cell1: cell_a port map(
            clk => clk, 
            s => c_s_1, c => xfer2_1, a => a(1), b => b, 
            c_out => c_s_1, s_out => xfer1_0 
            ); 

    cell0: cell_a port map(
            clk => clk, 
            s => c_s_0 , c => xfer1_0, a => a(0), b => b, 
            c_out => c_s_0, s_out => p 
            ); 
    process(clk) 
    begin 
     if(clk'event and clk = '1') then 
      if(rst = '1') then 
      --reset logic here. Magic happens and the circuit goes to all 0 
      end if; 
     end if; 
    end process; 
end Behavioral;

来源

2009-02-18 Paul Nathan