VHDL如何在本月结构代码

-2

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 


ENTITY aluall IS 
PORT(
     A:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     CLK:IN STD_LOGIC; 
     LOAD: in std_logic; 
     RESET: IN STD_LOGIC; 
     D:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 
     END aluall; 

ARCHITECTURE structual OF aluall IS 
SIGNAL finor,Rsub2,Rsub,Radd,Radd2,Radd1 : STD_LOGIC_VECTOR(7 DOWNTO 0); 
SIGNAL rAnd : STD_LOGIC_VECTOR(7 DOWNTO 0); 
signal rePiso : std_logic; 
SIGNAL fmulti : STD_LOGIC_VECTOR(15 DOWNTO 0); 
SIGNAL compare: STD_LOGIC_VECTOR(1 DOWNTO 0); 
signal repo: std_logic_vector(7 downto 0); 
signal choice: integer range 0 to 10; 


COMPONENT orGate 
PORT( A:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 
     END COMPONENT; 


COMPONENT andGate 
PORT( A:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 
     END COMPONENT; 

COMPONENT add1 
PORT(
    A : in std_logic_vector(7 downto 0); 
    C : out std_logic_vector(7 downto 0)); 
END COMPONENT; 

COMPONENT add2 

port(
    B : in std_logic_vector(7 downto 0); 
    C : out std_logic_vector(7 downto 0)); 

END COMPONENT; 



COMPONENT add 

port(
    A : in std_logic_vector(7 downto 0); 
    B : in std_logic_vector(7 downto 0); 
    C : out std_logic_vector(7 downto 0)); 
END COMPONENT; 



BEGIN --i want make choice menu for what go to output 
process(A,B,choice) 
begin 
if(choice = 0) then 
label0: andGate PORT MAP (A,B,rAnd); 
else 
label1: orGate PORT MAP (A,B,finor); 
end if; 
label2: add PORT MAP (A,B,Radd); 
label3: sub PORT MAP (A,B,Rsub); 
label4: sub2 PORT MAP (A,B,Rsub2); 



end structual;

我有错误非法顺序发言。

来源

2016-11-30 Soulis

格式的代码可以正确并给包括它指的是行号完整的错误消息。 –

现在我可以看到：您无法在流程中实例化组件。因此，您需要了解顺序语句和并发语句之间的区别，以及如何执行（a）顺序语句或（b）并发语句区域中的操作。但注意：你不能让门在运行时出现和消失。所以你可能需要两个门永久存在，并在他们的输出之间进行选择。 –

-1

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

ENTITY aluall IS 
PORT(
     A:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     code : std_logic_vector(3 downto 0); 
     CLK:IN STD_LOGIC; 
     D:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 
     END aluall; 

ARCHITECTURE structual OF aluall IS 
SIGNAL finor,Rsub2,Rsub,Radd,Radd2,Radd1 : STD_LOGIC_VECTOR(7 DOWNTO 0); 
SIGNAL rAnd : STD_LOGIC_VECTOR(7 DOWNTO 0); 
signal rePiso : std_logic; 
SIGNAL fmulti : STD_LOGIC_VECTOR(15 DOWNTO 0); 
SIGNAL compare: STD_LOGIC_VECTOR(7 DOWNTO 0); 
signal repo: std_logic_vector(7 downto 0); 


COMPONENT orGate 
PORT( A:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 
     END COMPONENT; 


COMPONENT andGate 
PORT( A:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 
     END COMPONENT; 

COMPONENT add1 
PORT(
    A : in std_logic_vector(7 downto 0); 
    C : out std_logic_vector(7 downto 0)); 
END COMPONENT; 

COMPONENT add2 

port(
    B : in std_logic_vector(7 downto 0); 
    C : out std_logic_vector(7 downto 0)); 

END COMPONENT; 

COMPONENT multi 
port(
    A : in std_logic_vector(7 downto 0); 
    B : in std_logic_vector(7 downto 0); 
    C : out std_logic_vector(15 downto 0)); 

END COMPONENT; 

COMPONENT add 

port(
    A : in std_logic_vector(7 downto 0); 
    B : in std_logic_vector(7 downto 0); 
    C : out std_logic_vector(7 downto 0)); 
END COMPONENT; 

COMPONENT sub 
port(
    A : in std_logic_vector(7 downto 0); 
    B : in std_logic_vector(7 downto 0); 
    C : out std_logic_vector(7 downto 0)); 

END COMPONENT; 

COMPONENT sub2 

port(
    A : in std_logic_vector(7 downto 0); 
    B : in std_logic_vector(7 downto 0); 
    C : out std_logic_vector(7 downto 0)); 

END COMPONENT; 

COMPONENT comparing 
port(
    A : in std_logic_vector(7 downto 0); 
    B : in std_logic_vector(7 downto 0); 
    C : out std_logic_vector(7 downto 0) 
); 
END COMPONENT; 

COMPONENT piso 
port(
CLK,LOAD : in std_logic; 
PI : in std_logic_vector(7 downto 0); 
SO : out std_logic 
); 
END COMPONENT; 


COMPONENT pipo 

port(
clk:in std_logic; 
pi: in std_logic_vector(7 downto 0); 
po:out std_logic_vector(7 downto 0) 

); 
end COMPONENT; 



begin 
label0: andGate PORT MAP (A,B,rAnd); 
label1: orGate PORT MAP (A,B,finor); 
label2: add PORT MAP (A,B,Radd); 
label3: sub PORT MAP (A,B,Rsub); 
label4: sub2 PORT MAP (A,B,Rsub2); 
label5: add1 PORT MAP (A,Radd1); 
label6: add2 PORT MAP (B,Radd2); 
label7: multi PORT MAP (A,B,fmulti); 
label8: comparing PORT MAP (A,B,compare); 
process(A,B,CLK,code) 
begin 




if (code = "0000") then 
D<= rAnd; 
elsif(code ="0001") then 
D<= finor; 
elsif(code ="0010") then 
D<=Rsub; 
elsif(code = "0011") then 
D<=Radd; 
elsif(code = "0100") then 
D<=Rsub; 
elsif(code = "0101") then 
D<=Rsub2; 
elsif(code = "0110") then 
D<=Radd1; 
elsif(code = "0111") then 
D<=Radd2; 
elsif(code = "1000") then 
D<=fmulti; 
else 
D<=compare; 
end if; 
end process; 



end structual;

我运行这段代码并始终如果和上次运行...为什么？

enter image description here

来源

2016-11-30 23:38:28 Soulis

这似乎是一个新问题，而不是前一个问题的答案。这不是一个聊天室。您需要将其作为新问题发布。 –

但是，您似乎认为您正在编写软件。你不是。 VHDL是_Hardware_描述语言。硬件不会'运行'，它始终存在。 andGate或Gate等是硬件子块。从你的踪迹来看，它看起来像你的子块没有逻辑。（把一个组件想象成一个IC插座，把一个实体想象成一个插入其中的IC）。我的猜测是你有很多没有绑定实体的组件。即你有许多没有集成电路的插座。这就是为什么你有很多'U''s。 –

为什么你使用_component instantiation_呢？ _Direct instantiation_更简单，更适合这种设计。 [http://electronics.stackexchange.com/questions/16692/vhdl-component-vs-entity](http://electronics.stackexchange.com/questions/16692/vhdl-component-vs-entity） –

VHDL如何在本月结构代码

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