如何在Verilog中将多个数组组合成一个数组？

这里是我的代码：如何在Verilog中将多个数组组合成一个数组？

module MIPS_Processor(); 
    reg [7:0] mem [0:4095];  // 4K memory cells that are 8 bits wide 
    reg [7:0] code[0:1023];  // 1K memory cells that are 8 bits wide 
    reg [31:0] registers[0:31]; // 32 registers that are 32 bits wide 
    reg [31:0] PC;    // The program counter 

    initial 
     begin 
      PC = 0; 
     end 

    always 
     begin 
      // 1. Fetch an instruction from memory 
      bit [31:0] instruction = {{code[PC * 8 + 7:PC * 8 + 0]}, 
            {code[(PC + 1) * 8 + 7:(PC + 1) * 8 + 0]}, 
            {code[(PC + 2) * 8 + 7:(PC + 2) * 8 + 0]}, 
            {code[(PC + 3) * 8 + 7:(PC + 3) * 8 + 0]}}; 

      // 2. Increment the program counter register (by the instruction length) 
      PC = PC + 4; 

      // Rest of the code 

    end 
endmodule

我怎么能结合4个阵列成一个阵列来从该代码的指令？上面的代码不能编译！

编辑：

代码更改为以后有什么建议@toolic：

bit [31:0] instruction = { 
        code[PC + 0], 
        code[PC + 1], 
        code[PC + 2], 
        code[PC + 3] 
};

的是，它不会编译：

采用Xilinx：

========================================================================= 
*       HDL Compilation        * 
========================================================================= 
Compiling verilog file "MIPS_Processor.v" in library work 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 expecting ']', found ':' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '=' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '{' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 40 expecting '.', found ',' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 41 expecting '.', found ',' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 42 expecting '.', found ',' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 44 expecting '.', found '}' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: '=' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: 'PC' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'end', found '+' 
Module <MIPS_Processor> compiled 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'endmodule', found '4' 
Analysis of file <"MIPS_Processor.prj"> failed. 
--> 

Total memory usage is 274336 kilobytes 

Number of errors : 11 ( 0 filtered) 
Number of warnings : 0 ( 0 filtered) 
Number of infos : 0 ( 0 filtered) 


Process "Synthesize - XST" failed

使用Verilogger极端：

enter image description here

来源

2012-03-16 Eng.Fouad

作为题外话，MIPS使用字寻址的存储器与字节使能，因此改变你的代码，以便它模拟你的Verilog内存作为一个单词阵列将更好地匹配硬件，并将使检测未对齐的内存访问更容易在其余的Verilog代码。 – markgz 2012-03-16 23:51:05

为了形成从code存储器的连续4个字节的指令字：

// 1. Fetch an instruction from memory 
bit [31:0] instruction = { 
         code[PC + 0], 
         code[PC + 1], 
         code[PC + 2], 
         code[PC + 3] 
};

来源

2012-03-16 23:43:20 toolic

+1感谢您的回答，但它不能编译:( – 2012-03-17 00:08:13

它使用2个不同的模拟器编译我 – toolic 2012-03-17 00:55:20

请参阅更新 – 2012-03-17 01:06:36

如何在Verilog中将多个数组组合成一个数组？

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