我想写一个VHDL模块,但我有一个if语句的问题。很可能这是一个愚蠢的错误,但由于我对VHDL非常陌生,我无法弄清楚这个问题。这里是我的代码:意外的TICK错误
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity binary_add is
port(n1 : in std_logic_vector(3 downto 0);
n2 : in std_logic_vector(3 downto 0);
segments : out std_logic_vector(7 downto 0);
bool : out bit;
o : out std_logic_vector(3 downto 0);
DNout : out std_logic_vector(3 downto 0));
end binary_add;
architecture Behavioral of binary_add is
begin
process(n1, n2)
begin
o <= n1 + n2;
if(o = '1010') then
bool <= '1';
else
bool <= '0';
end if;
end process;
end Behavioral;
我从if语句的第一行得到如下答案:
ERROR:HDLParsers:## - "C:/Xilinx/12.3/ISE_DS/ISE/.../binary_add.vhd" Line ##. parse error, unexpected TICK
我在做什么错?
嗨。如果答案帮助你,请注册。接受最有用的! – Marty 2010-11-03 13:56:06