MAX 10 ADC with VHDL/Quartus Prime Lite代码优化

首先，我不得不说我是VHDL的补充初学者，所以如果它提出了一个真正愚蠢的问题，我想提前致歉。我试图让ADC软IP工作。我只想使用ADC，所以没有FIFO或其他任何东西。因此我使用qsys文件生成IP核并将其包含到我的项目中。我还用预分频器激活了通道8。我试图读取连接到通道8的可变电阻的值，并打印出LED的5个最高有效位。 case语句应创建激活adc所需的模式，如MAX 10 ADC指南中给出的。MAX 10 ADC with VHDL/Quartus Prime Lite代码优化

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 



entity main is 
    port (CLK_50 : in std_logic; 
      LEDR : out std_logic_vector(4 downto 0)); 
end; 


architecture behave of main is 

    signal Cnt : integer := 0; 
    signal pCnt : integer := 0; 

    signal lock : std_logic; 
    signal CLK_10 : std_logic; 
    signal CLK_1 : std_logic; 
    signal set : std_logic ; 

    signal RESET : std_logic ; 

    signal CMDVal : std_logic; 
    signal CMDCH : std_logic_vector (4 downto 0); 
    signal CMDSOP : std_logic; 
    signal CMDEOP : std_logic; 
    signal CMDRDY : std_logic; 
    signal RESVal : std_logic; 
    signal RESCH : std_logic_vector (4 downto 0); 
    signal RESData : std_logic_vector (11 downto 0); 
    signal RESSOP : std_logic; 
    signal RESEOP : std_logic; 

    component myadc is 
     port (
      clock_clk    : in std_logic      := 'X';    -- clk 
      reset_sink_reset_n  : in std_logic      := 'X';    -- reset_n 
      adc_pll_clock_clk  : in std_logic      := 'X';    -- clk 
      adc_pll_locked_export : in std_logic      := 'X';    -- export 
      command_valid   : in std_logic      := 'X';    -- valid 
      command_channel  : in std_logic_vector(4 downto 0) := (others => 'X'); -- channel 
      command_startofpacket : in std_logic      := 'X';    -- startofpacket 
      command_endofpacket : in std_logic      := 'X';    -- endofpacket 
      command_ready   : out std_logic;          -- ready 
      response_valid   : out std_logic;          -- valid 
      response_channel  : out std_logic_vector(4 downto 0);      -- channel 
      response_data   : out std_logic_vector(11 downto 0);     -- data 
      response_startofpacket : out std_logic;          -- startofpacket 
      response_endofpacket : out std_logic           -- endofpacket 
     ); 
    end component myadc; 

begin 

    CMDCH <= "01000"; 
    RESET <= '0'; 
    set <= '1'; 

    mPLL : entity work.pll 
     port map(
     areset => set, 
     inclk0 => CLK_50, 
     c0 => CLK_10, 
     c1 => CLK_1, 
     locked => lock 
    ); 


    mADC : component myadc 
     port map (
      clock_clk    => CLK_50,     --   clock.clk 
      reset_sink_reset_n  => RESET,      --  reset_sink.reset_n 
      adc_pll_clock_clk  => CLK_10,     -- adc_pll_clock.clk 
      adc_pll_locked_export => lock,       -- adc_pll_locked.export 
      command_valid   => CMDVal,     --  command.valid 
      command_channel  => CMDCH,     --    .channel 
      command_startofpacket => CMDSOP,     --    .startofpacket 
      command_endofpacket => CMDEOP,     --    .endofpacket 
      command_ready   => CMDRDY,     --    .ready 
      response_valid   => RESVal,     --  response.valid 
      response_channel  => RESCH,      --    .channel 
      response_data   => RESData,    --    .data 
      response_startofpacket => RESSOP,     --    .startofpacket 
      response_endofpacket => RESEOP     --    .endofpacket 
     ); 

process 
begin 

    wait until rising_edge(CLK_50); 

    pCnt <= pCnt + 1; 

    case pCnt is 
     when 1 => CMDSOP <= '1'; 
        CMDVal <= '1'; 
     when 114 => CMDRDY <= '1'; 
     when 115 => CMDSOP <= '0'; 
         CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 214 => CMDRDY <= '1'; 
     when 215 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 314 => CMDRDY <= '1'; 
     when 315 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 414 => CMDRDY <= '1'; 
     when 415 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 514 => CMDRDY <= '1'; 
     when 515 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 614 => CMDRDY <= '1'; 
     when 615 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 714 => CMDRDY <= '1'; 
     when 715 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 814 => CMDRDY <= '1'; 
     when 815 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 914 => CMDRDY <= '1'; 
     when 915 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 1014 => CMDRDY <= '1'; 
     when 1015 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7);  
     when 1114 => CMDRDY <= '1'; 
     when 1115 => CMDRDY <= '0'; 
         CMDEOP <= '1'; 
     when 1116 => CMDEOP <= '0'; 
         CMDVal <= '0'; 


     when 2000 => pCnt <= 0; 
     when others => Cnt <= pCnt ; 
    end case; 
end process; 

end;

但是编译Quartus时总是会删除我所有的代码。所以最后它将LED拉到GND，既不使用ADC也不使用PLL。如果任何人有一个想法，我会非常感谢，如果你能告诉我什么exaclty即时做错了。

此致敬礼。

编辑：我没有足够清楚地描述我的问题。它确实合成正确，但它认为pll不是必需的，因此将其删除，使adc ip核心没有时钟，因此也将其删除。的错误是：

Warning (14284): Synthesized away the following node(s): 
    Warning (14285): Synthesized away the following RAM node(s): 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[0]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[1]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[2]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[3]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[4]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[5]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[6]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[7]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[8]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[9]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[10]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[11]" 
Warning (14284): Synthesized away the following node(s): 
    Warning (14285): Synthesized away the following RAM node(s): 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[0]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[1]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[2]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[3]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[4]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[5]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[6]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[7]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[8]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[9]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[10]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[11]" 
Warning (14284): Synthesized away the following node(s): 
    Warning (14285): Synthesized away the following PLL node(s): 
     Warning (14320): Synthesized away node "mpll:myPLL|altpll:altpll_component|mpll_altpll:auto_generated|wire_pll1_clk[0]"

来源

2017-02-20 nuclear

当您的逻辑在优化期间被吃掉并且您的输出连接到导轨时，它通常是逻辑设计错误或工具使用错误的标志。在这种情况下，集中在用于驱动LEDR值的myadc的ResData上。除了myadc可能存在的逻辑问题之外，它还可以被解开，导致ResData不被驱动，整个设计的其余部分被吃掉（LEDR是唯一的输出）。您需要在综合期间检查控制台输出（或日志）是否有警告和错误。 – user1155120

是的，我意识到问题是输出不被驱动，所以我试图将adc的数据保存在一个单独的std_logic_vector中，并在每个时钟周期驱动输出，但是这并没有改变问题。缺点是我不知道如何改变adc逻辑内的任何东西，因为它的altera ip核心。我只能通过样本存储找到adc控件的教程。据我了解altera文件驱动adc的逻辑应该是正确的，但可悲的是我不能确认它。 – nuclear

你的读者似乎不可能窥探黑匣子，并告诉你什么是错的，而不会被同样的咬伤。您似乎在生成过程中正在处理IP内核配置。你说过你没有使用FIFO，在myadc组件声明中有一个PLL。 – user1155120

在VHDL（基本上在所有的硬件描述语言），你要记住，你的代码必须synthetizable：它来形容你的可编程组件可用的硬件组件。在你的过程中情况并非如此。

以下行：wait until rising_edge(CLK_50);由于wait语句而无法合成。

要创建你需要这个顺序的过程：

my_seq_proc : process (clk, rst) 
begin 
    if (rst = '1') then 
     ... -- reset your signals 
    elsif (rising_edge(clk)) then 
     ... -- what you need to do 
    end if; 
end process;

请注意，您不一定要使用一个复位信号。此外，请注意，您需要在时钟（clk_50）和可能的复位信号的过程声明(clk, rst)中使用灵敏度列表。

我还没有检查是否有另一个错误。你应该尝试先做到这一点。

来源

2017-02-20 15:54:06

推荐的编码风格与支持的推理寄存器风格之间存在差异。建议的样式可在第1卷设计和综合手册中找到。支持的样式位于撤消的IEEE Std 1076.6-2004 IEEE标准VHDL寄存器传输级别（RTL）综合中。在这种特殊情况下，6.1.3.2使用单个等待语句的边缘敏感存储与OP的使用相匹配。预计Altera的综合工具将符合撤回的IEEE标准。 – user1155120

据我所知等到rising_edge（clk）是一个完全有效的选项，只要你不想重置。反正它没有问题之前合成过。然而，虽然syhetizing由于某种原因删除了pll，所以当然所有的逻辑根本不起作用。但我也改变了你如何推荐它，但它仍然无法正常工作。 – nuclear

不知道“等到”是否被Altera支持进行合成。那我很抱歉。 –

MAX 10 ADC with VHDL/Quartus Prime Lite代码优化

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