每次我模拟下面的代码时,我的输出都是未定义的,我不知道为什么。我在代码和模拟中都有数字库。如果有人能帮助让我知道。此外,在模拟输入成为00000..000而不是15和3未定义的输出
模块代码的输入:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity EXPONENT_FUNCTION is
Port (A : in STD_LOGIC_VECTOR (23 downto 0);
B : in STD_LOGIC_VECTOR (23 downto 0);
O : out STD_LOGIC_VECTOR (47 downto 0));
end EXPONENT_FUNCTION;
architecture Behavioral of EXPONENT_FUNCTION is
signal AIN, BIN, F : integer;
signal u : std_logic_vector (47 downto 0);
begin
AIN <= to_integer(signed (A));
BIN <= to_integer(signed (B));
F <= ((AIN)**(BIN));
u <= std_logic_vector(to_signed(F, 48));
O <= u;
end Behavioral;
模拟代码:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY EXPONENT_TEST IS
END EXPONENT_TEST;
ARCHITECTURE behavior OF EXPONENT_TEST IS
COMPONENT EXPONENT_FUNCTION
PORT(
A : IN std_logic_vector(23 downto 0);
B : IN std_logic_vector(23 downto 0);
O : OUT std_logic_vector(47 downto 0)
);
END COMPONENT;
signal A : std_logic_vector(23 downto 0) := (others => '0');
signal B : std_logic_vector(23 downto 0) := (others => '0');
signal O : std_logic_vector(47 downto 0);
BEGIN
uut: EXPONENT_FUNCTION PORT MAP (
A => A,
B => B,
O => O
);
stim_proc: process
begin
A <= "000000000000000000001111";
B <= "000000000000000000000011";
wait for 100 ns;
wait;
end process;
END;
如果模拟自身上面的代码,它的输出将是不确定的,因为不被驱动的输入。您需要在您的问题中包含测试平台的代码。 (请参阅[MCVE](http://stackoverflow.com/help/mcve))。 –
我用模拟代码 – Mrbeck101