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我必须比较功能代码和rtl代码。下面的代码被写为一个16位输入的二分量结构代码。我试图编写以下电路:VHDL中的程序返回未知
在这里,我所包围的代码和测试台:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity two_s_complement_16bit_rtl is
Port (A : in STD_LOGIC_VECTOR (15 downto 0);
Cout : out STD_LOGIC_VECTOR (15 downto 0):= (others => '0'));
end two_s_complement_16bit_rtl;
architecture Behavioral of two_s_complement_16bit_rtl is
procedure two_s_complement (
A : in std_logic;
B : in std_logic;
C : out std_logic;
cout : out std_logic;
cin : in std_logic) is
begin
cout := ((not A) and B) xor (((not A) xor B) and cin);
end procedure;
begin
process (A)
variable temp_C, temp_Cout: STD_LOGIC_VECTOR(15 downto 0);
constant B_0 : STD_LOGIC := '1';
constant B_1 : STD_LOGIC := '0';
begin
for i in 0 to 15 loop
if (i = 0) then
two_s_complement (A(i), B_0 ,temp_C(i) ,temp_Cout(i) , B_1);
else
two_s_complement (A(i), B_1 ,temp_C(i) ,temp_Cout(i) , temp_C(i-1));
end if;
end loop;
Cout <= temp_Cout;
end process;
end Behavioral;
的测试台:
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity two_s_complement_16bit_rtl_tb is
end;
architecture bench of two_s_complement_16bit_rtl_tb is
component two_s_complement_16bit_rtl
Port (A : in STD_LOGIC_VECTOR (15 downto 0);
Cout : out STD_LOGIC_VECTOR (15 downto 0):= (others => '0'));
end component;
signal A: STD_LOGIC_VECTOR (15 downto 0);
signal Cout: STD_LOGIC_VECTOR (15 downto 0):= (others => '0');
begin
uut: two_s_complement_16bit_rtl port map (A => A,
Cout => Cout);
stimulus: process
begin
-- Put initialisation code here
A <= "0100010010110000";
wait for 10 ns;
A <= "0011000011110111";
wait for 10 ns;
A <= "0000000000000001";
wait for 10 ns;
A <= "0011110010110011";
wait for 10 ns;
A <= "0010000100100001";
wait for 10 ns;
A <= "0001011100100011";
wait for 10 ns;
A <= "1011000110111001";
wait for 10 ns;
A <= "0000001011001010";
wait for 10 ns;
A <= "0011110110100000";
wait for 10 ns;
A <= "0100000111111000";
wait for 10 ns;
A <= "1011111001111100";
wait for 10 ns;
A <= "1111000110000001";
wait for 10 ns;
A <= "0111000111001011";
wait for 10 ns;
A <= "1011011101101010";
wait for 10 ns;
A <= "1111001001010111";
wait for 10 ns;
-- Put test bench stimulus code here
wait;
end process;
end;
我已经考虑了第一个单元的三个输入,但是其中的两个Cin和B具有代码中提到的恒定值,但是输出是未知的。
'return(-A);'完成了工作。 –
正如后文所述,我必须将rtl与功能进行比较,这就是为什么我编写了这些代码。 – syzd
您的循环过程调用不执行显示的电路。该过程应该实现一个完整的加法器,而不是例如分配C输出(传播'U's)。您在过程调用中也存在位置关联错误,在使用命名关联时很容易出现。当i = 0时,cin输入应该与temp_cout(i-1)相关联。另外'cout <= temp_c; - WAS temp_cout;'。可以反转A并描述一个增量,消除B输入和不必要的逻辑。 – user1155120