2014-12-02 48 views
-1

我的代码描述了一个FSM来控制交通信号灯。有四个州,每个州的持续时间都不相同。计数器数字扼腕

只要计数器等于1,计数器就需要多一个时钟才能切换到下一个值。例如,在状态1,计数器被编程为从4到1计数。每个值只需要一个时钟到 切换到下一个状态,当状态变为下一个状态时。但是当计数器等于1时,需要两个时钟才能更改。

我的程序如下。该计数器在always块的底部实现:

module HW3(times,A,B,clk,rst,iHand,iChang,s1); 

input clk,rst; 
output reg [2:0]A,B; 
wire oclk;//new freq 
reg [2:0] count1,count2,count3,count4;//count times 
reg [2:0]times; 
reg temp;//control the switch 
parameter [2:0]state1=3'd0,state2=3'd1,state3=3'd2,state4=3'd3; 

[email protected](posedge clk or negedge rst ) 
    begin 


       if(!rst) 
        begin 
         s1<=state1; 
         A<=3'b0; 
         B<=3'b0; 
         count1<=3'd4; 
         count2<=3'd2; 
         count3<=3'd3; 
         count4<=3'd2; 
         temp<=1'b1; 
        end 
       else 
        begin 
         if(temp==1) 
          begin 
           temp<=1'b0; 
           case(s1) 
            state1: 
             begin 
              times<=count1; 
              A<=3'b001; 
              B<=3'b100; 
              s1<=state2; 
             end 
            state2: 
             begin 
              times<=count2; 
              A<=3'b010; 
              B<=3'b100; 
              s1<=state3;    
             end 
            state3: 
             begin 
              times<=count3; 
              A<=3'b100; 
              B<=3'b001; 
              s1<=state4; 

             end 
            state4: 
             begin 
              times<=count4; 
              A<=3'b100; 
              B<=3'b010; 
              s1<=state1; 
             end 
            default: 
             begin 
              A<=3'b000; 
              B<=3'b000; 
             end 
            endcase 
          end 
         else 
          begin 
           if(times>1) 
            times<=times-1; 
           else if(times==1) 
            begin 
             temp<=1'b1;//can't count averagely 

            end 
          end 
        end 

    end 
endmodule 
+0

您的代码有很多很多问题的价值。 [Read This!](http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf) – N8TRO 2014-12-02 07:44:49

+0

我已经修复了你说的问题,但延迟仍然存在 – 2014-12-02 11:22:46

+0

我已将它设置在[EDA Playground](http ://www.edaplayground.com/x/8Ap)。它看起来像所有的国家需要一个额外的时钟来过渡。将'state'和'times'添加到波形视图。 – Morgan 2014-12-02 12:06:29

回答

0
Modify the code at the bottom of the always clock as: 

if(times>2) 
times<=times-1; 
     else if(times==2) 
       begin 
         times=times-1; 
         temp<=1'b1;//can't count averagely 

         end   

只是让次计数2,因为如果让它计数到1时,程序将再次进入,如果

块在下一个时钟,但并没有改变时代的价值,并作出时间= 1不变

多一个时钟