计数器系统verilog代码

Question

我有这个计数器的问题。输出全是xxxxxxxx，我知道我应该将count的初始值和溢出设置为0，但它会给出错误。这是代码：

// Code your design here 
module counter (in, start, count, clk, overflow); 

input [3:0] in; 
input clk; 
input start; 
output reg [7:0] count; 
output reg overflow; 
//reg count; 
//count =0; 
//overflow=0; 
always @ (posedge clk) 
    begin 
    if (start) begin 
     count <= 8'b0; 
     overflow <= 1'b0; 
    end 

    else if (in == 4'b0101) begin 
     count <= count+1; 
    end 
    if (count == 4'b1111) begin 
     overflow <=1'b1; 
    end 
    end 

endmodule 

这是测试平台：

// Code your testbench here 
// or browse Examples 
module tb(); 

    reg [3:0] in; 
    reg clk,start; 
    wire [7:0] count; 
    reg overflow = 1'b0; 

    initial begin 

    $display ("time\t clk start in count overflow"); 
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow); 

    clk=0; 
    in=0; 
    start=0; 
    // overflow=0; 
    // count=0; 

    #5 in=4'd1; 
    #5 in=4'd5; 
    #5 in=4'd4; 
    #5 in=5'd5; 
    #5 in=4'd1; 
    #5 in=4'd5; 
    #5 in=4'd4; 
    #5 in=5'd5; 
    #5 in=4'd1; 
    #5 in=4'd5; 
    #5 in=4'd4; 
    #5 in=5'd5; 
    #5 in=4'd1; 
    #5 in=4'd5; 
    #5 in=4'd4; 
    #5 in=5'd5; 
    #50 $finish; 

    end 

    always #5 clk=~clk; 

    counter u0(.*); 

endmodule 

我知道这是一个简单的问题，但我很感激，如果你们帮帮忙。

Answer 1

有两个问题需要解决。

1）巧合地in = 5仅在时钟的负边沿期间设置。这是因为clk周期是＃10，并且tb代码每＃5改变“in”值。当计数器检查posedge中的in值时，它忽略in = 5。时间段需要＃10或TB在设置信号“in”之前可以等待clk的时间。 2）需要为计数器设置开始重置，否则计数= x（未知）和计数+ 1 => x + 1的值等于x。因此，柜台不会增加，并始终保持x。

更新后的tb如下。

module tb(); 

    reg [3:0] in; 
    reg clk,start; 
    wire [7:0] count; 
    reg overflow = 1'b0; 

    initial begin 

    $display ("time\t clk start in count overflow"); 
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow); 

    clk=0; 
    in=0; 
    start=0; 
    // overflow=0; 
    // count=0; 

    #10 start = 1'b1; // reset counter 
    #10 start = 1'b0; 
    #10 in=4'd1; 
    #10 in=4'd5; 
    #10 in=4'd4; 
    #10 in=5'd5; 
    #10 in=4'd1; 
    #10 in=4'd5; 
    #10 in=4'd4; 
    #10 in=5'd5; 
    #10 in=4'd1; 
    #10 in=4'd5; 
    #10 in=4'd4; 
    #10 in=5'd5; 
    #10 in=4'd1; 
    #10 in=4'd5; 
    #10 in=4'd4; 
    #10 in=5'd5; 
    #50 $finish; 

    end 

    always #5 clk=~clk; 

    counter u0(.*); 

initial // Dump waveform for debug 
$dumpvars; 

endmodule 

您可以使用$ dumpvars命令转储波形以进行调试。

替代代码（使用posedge事件驱动的测试台数据）

// Code your testbench here 
// or browse Examples 
module tb(); 

    reg [3:0] in; 
    reg clk,start; 
    wire [7:0] count; 
    reg overflow = 1'b0; 

    initial begin 

    $display ("time\t clk start in count overflow"); 
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow); 

    clk=0; 
    in=0; 
    start=0; 
    // overflow=0; 
    // count=0; 

    @(posedge clk) start = 1'b1;// reset counter 
    @(posedge clk) start = 1'b0; 
    @(posedge clk) in=4'd1; 
    @(posedge clk) in=4'd5; 
    @(posedge clk) in=4'd4; 
    @(posedge clk) in=5'd5; 
    @(posedge clk) in=4'd1; 
    @(posedge clk) in=4'd5; 
    @(posedge clk) in=4'd4; 
    @(posedge clk) in=5'd5; 
    @(posedge clk) in=4'd1; 
    @(posedge clk) in=4'd5; 
    @(posedge clk) in=4'd4; 
    @(posedge clk) in=5'd5; 
    @(posedge clk) in=4'd1; 
    @(posedge clk) in=4'd5; 
    @(posedge clk) in=4'd4; 
    @(posedge clk) in=5'd5; 
    #50 $finish; 

    end 

    always #5 clk=~clk; 

    counter u0(.*); 

initial 
$dumpvars; 

endmodule