VHDL中的信号分配？严重警告

Question

有一些严重警告，但我不知道它们到底在哪里，甚至如何摆脱它们...... 警告说某些行有语法错误，但我只是没有看到它们:( 标志着我在该行

顺便说结束与--ERR线，是RAM块的确定的定义是什么？

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

-- Uncomment the following library declaration if using 
-- arithmetic functions with Signed or Unsigned values 
--use IEEE.NUMERIC_STD.ALL; 

-- Uncomment the following library declaration if instantiating 
-- any Xilinx leaf cells in this code. 
--library UNISIM; 
--use UNISIM.VComponents.all; 


Library UNISIM; 
use UNISIM.vcomponents.all; 
library UNIMACRO; 
use unimacro.Vcomponents.all; 

entity Buffer_BRAM is 
    generic(ADDR : integer :=32); 
    Port (clk : in STD_LOGIC; 
     rst : in STD_LOGIC; 
     data_in : in STD_LOGIC_VECTOR (31 downto 0); 
     data_out : out STD_LOGIC_VECTOR (31 downto 0)); 
end Buffer_BRAM; 

architecture Behavioral of Buffer_BRAM is 

    component BRAM_32_16K 
    generic(
     PTR1 : integer := 0; 
     PTR2 : integer := 1024; 
     PTR3 : integer := 2048; 
     PTR4 : integer := 4096 
    ); 
    PORT(
     clka : IN STD_LOGIC; 
     rsta : IN STD_LOGIC; 
     wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
     addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
     dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
     douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 

     clkb : IN STD_LOGIC; 
     rstb : IN STD_LOGIC; 
     web : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
     addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
     dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
     doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 
    ); 

    end COMPONENT; 

    signal input1 : std_logic_vector(31 downto 0) := "10101100010100111010110001010011"; 
    signal input2 : std_logic_vector(31 downto 0) := "10101100010100111010110001010011"; 

    signal ptr_read, ptr_write : std_logic_vector(ADDR-1 downto 0) := (others =>'0'); 

    signal WEA, WEB : std_logic_vector(3 downto 0) :=(others=>'1'); 
    signal dinb, doutb, dina, douta : std_logic_vector(31 downto 0) := (others => '0'); 
    signal rsta, rstb :std_logic := '0' ; 
    signal num1, num2 : std_logic_vector(15 downto 0) := (others => '0'); 

    begin process(clka, rsta, ptr_write) 
    dina := input1;      --ERR 
    ptr_write <= ptr_write + 4; 
    end 

    begin process(clkb, rstb, ptr_write) 
    dinb := input2;      --ERR 
    ptr_write <= ptr_write + 4; 
    end 

    begin process(clk, rst)    --ERR 
    doutb <= ptr_read;     --ERR 
    num2 <= doutb; 
    ptr_read <= ptr_read - 1; 
    end 

end Behavioral       --ERR 

Answer 1

你需要定义你的信号，你的组件前 the architecture begin。试试这个：

architecture Behavioral of Buffer_BRAM is 

    component BRAM_32_16K 
    generic(
     PTR1 : integer := 0; 
     PTR2 : integer := 1024; 
     PTR3 : integer := 2048; 
     PTR4 : integer := 4096 
    ); 
    PORT(
     clka : IN STD_LOGIC; 
     rsta : IN STD_LOGIC; 
     wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
     addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
     dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
     douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 

     clkb : IN STD_LOGIC; 
     rstb : IN STD_LOGIC; 
     web : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
     addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
     dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
     doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 
    ); 

    end COMPONENT; 

    signal input1 : std_logic_vector(31 downto 0) := "10101100010100111010110001010011"; 
    signal input2 : std_logic_vector(31 downto 0) := "10101100010100111010110001010011"; 

    signal ptr_read, ptr_write : std_logic_vector(ADDR-1 downto 0) := (others =>'0'); 

    signal WEA, WEB : std_logic_vector(3 downto 0) :=(others=>'1'); 
    signal dinb, doutb, dina, douta : std_logic_vector(31 downto 0) := (others => '0'); 
    signal rsta, rstb :std_logic := '0' ; 
    signal num1, num2 : std_logic_vector(15 downto 0) := (others => '0'); 

    begin -- ONLY ONE BEGIN IS USED, BEGINS THE ARCHITECTURE 

    process(clka, rsta, ptr_write) 
    begin -- OTHER BEGINS ARE FOR YOUR PROCESSES 
    dina := input1;      --ERR 
    ptr_write <= ptr_write + 4; 
    end 

    process(clkb, rstb, ptr_write) 
    begin -- OTHER BEGINS ARE FOR YOUR PROCESSES 
    dinb := input2;      --ERR 
    ptr_write <= ptr_write + 4; 
    end 

    process(clk, rst)    --ERR 
    begin -- OTHER BEGINS ARE FOR YOUR PROCESSES 
    doutb <= ptr_read;     --ERR 
    num2 <= doutb; 
    ptr_read <= ptr_read - 1; 
    end 

end Behavioral       --ERR 

作为一个方面说明，我不认为这些过程中的任何一个都会做你打算做的事情。他们都没有钟表！他们应该是这个样子：

process(clk)    --ERR 
    begin 
    if rising_edge(clk) then 
     doutb <= ptr_read;     --ERR 
     num2 <= doutb; 
     ptr_read <= ptr_read - 1; 
    end if; 
    end 

至于另一个方面说明，你不能做你的信号数学，而不包括其他包文件。您应该在文件顶部包含numeric_std。

发现更多的东西错了。请勿在此处使用:=赋值运算符。这仅适用于变量和信号初始化。这会导致编译错误。