VHDL：如何读取/写入RAM中的16位数据，每个地址8位

Question

我有一个VHDL代码用于读取和写入8位数据到每个地址8位的RAM，但我需要更改该代码用于以每个地址8位的数据读/写16位数据到RAM。 可以做些什么改变？

初始代码我有是：

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

entity RAM is 
port(address: in std_logic_vector(0 to 15); 
    datain: in std_logic_vector(7 downto 0); 
    dataout: out std_logic_vector(7 downto 0); 
    WE, CS, OE: in std_logic); 
end entity RAM; 

architecture behavior6 of RAM is 
type RAM_type is array (0 to 2**16) of std_logic_vector(7 downto 0); 
signal RAM1: RAM_type; 

begin 
process (address, CS, WE, OE) 
begin 
dataout <= (others => 'Z'); --chip is not selected (this is the first row of the T.T) 
if (CS = '0') 
then 

if WE= '0' then --we want to write 
RAM1(to_integer(unsigned(address))) <= datain; 
end if; 

if WE= '1' and OE= '0' 
then--we want to read 
dataout <= RAM1(to_integer(unsigned(address))); 
else 
dataout <= (others => 'Z'); 
end if; 
end if; 
end process; 
end behavior6; 

Answer 1

在两个地址尝试此代码

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 
entity RAM is 
port(address: in std_logic_vector(7 down to 0); 
     datain: in std_logic_vector(15 downto 0); 
     dataout: out std_logic_vector(15 downto 0); 
     WE, CS, OE: in std_logic); 
end entity RAM; 

architecture behavior6 of RAM is type RAM_type is array (255 down to 0) of std_logic_vector(15 downto 0); signal RAM1:memory:=(others=>"0000000000000000"); begin process (address, CS, WE, OE) variable a:integer range 0 to 255; begin a:=conv_integer(address); if (CS = '0') then if WE= '0' then RAM1(a)<=datain; end if; if WE= '1' and OE= '0' then dataout<=RAM1(a); end if; end if; end process; end behavior6;