信号<n1<1> _IBUF>是不完整的

Question

我想写一个VHDL模块，但我有一些输入的问题，这里是我的代码：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
--use ieee.std_logic_arith.all; 
use ieee.std_logic_signed.all; 


entity binary_add is 
    port(n1 : in std_logic_vector(3 downto 0); 
    n2 : in std_logic_vector(3 downto 0); 
    segments : out std_logic_vector(7 downto 0); 
    DNout : out std_logic_vector(3 downto 0)); 

end binary_add; 

architecture Behavioral of binary_add is 
begin 

DNout <= "1110"; 

process(n1, n2) 

variable x: integer; 


begin 

x:= conv_integer(n1(3)&n1(2)&n1(1)&n1(0)) + conv_integer(n2(3)&n2(2)&n2(1)&n2(0)); 

if(x = "0") then 

segments <= "10000001"; 

elsif(x = "1") then 

segments <= "11001111"; 

else 

segments <= "00000000"; 

end if; 

end process; 

end Behavioral; 

我得到这些错误：

WARNING:PhysDesignRules:367 - The signal <n1<1>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:PhysDesignRules:367 - The signal <n1<2>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:PhysDesignRules:367 - The signal <n1<3>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:PhysDesignRules:367 - The signal <n2<1>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:PhysDesignRules:367 - The signal <n2<2>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:PhysDesignRules:367 - The signal <n2<3>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:Par:288 - The signal n1<1>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:288 - The signal n1<2>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:288 - The signal n1<3>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:288 - The signal n2<1>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:288 - The signal n2<2>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:288 - The signal n2<3>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. 

错误似乎很复杂，但实际上它说，我认为，无法路由我的n1和n2信号的其他3个输入。我不明白为什么会发生这种情况，但我只想将n1和n2带符号的数字总和显示为7段显示。如果有人能帮我弄清楚这个问题，我会很感激。

Answer 1

第一：不要使用std_logic_arith或std_logic_signed - 我已经written about why not。第二：你已经创建了一个异步进程，这在FPGA中是非常好的练习，这些练习是以同步的方式使用（以及工具希望你使用的）。创建一个时钟输入并使用它。你可以异步，但直到你真的知道你在做什么，避免它。一旦你真的知道你在做什么，你可能会避免它，因为你知道它会是多么讨厌:)

我会让我的端口signed类型和use ieee.numeric_stdd.all;。甚至在输入端口上使用integer类型。如果这是顶级块，你需要把一个包装周围采取的最引脚std_logic_vectors，把它们变成整数，并将它们送入你上面写的块：

n1 <= to_integer(signed(n1_pins)); 

然后你需要做这样的事情...

architecture Behavioral of binary_add is 
begin 
DNout <= "1110"; 
process(clk) 
    variable x: integer; 
begin 
    x:= n1+n2; 
    case x 
    when 0 => segments <= "10000001"; 
    when 1 => segments <= "11001111"; 

等

或者创建一个常量数组整数转换成7段，做

segments <= int_to_7seg(x);