我想实例化我的计数器模块的三个实例。但是,赛灵思将仅为我实例化一个计数器,而不是三个计数器。有人知道为什么吗?在RTL原理图中,第二个两个计数器在其框图中直接连接到地,即没有实现它们的逻辑。我的本地参数是否正确声明?Verilog Xilinx - FPGA板 - 无法实例化三个计数模块的多个实例
我真的很感谢你的帮助。我一直在盯着这个问题好几个小时。
非常感谢您的帮助。真的很感激。
//Top Level Module:
`timescale 1ns/1ps
//Top Level Wrapper module
module topWrapper(input CCLK, input reset, output clk, output max_tick_Green, output max_tick_Red, output max_tick_Amber);
localparam
M_Green = 5;
M_Red = 3;
M_Amber = 2;
//Frequency scaling of CCLK
//clk is used in the traffic light module and is a scaled version of CCLK
//CCLK: Frequency = 50MHz, Period = 20ns
//clk = Frequency = 1Hz, Period = 1s
//clkscale (frequency scaling parameter) = 1s/20ns = 5x10^7
clock clockScalingModule (CCLK, 50000000, clk);
//Counter for green light
//In traffic light sequence, change from green to amber after 12 clock cycles = 120s = 2mins
counter #(.M(M_Green)) countGreen
(.clk(clk), .reset(reset), .state(1), .max_tick(max_tick_Green));
//Counter for red light
//In traffic light sequence, change from green to amber after 12 clock cycles = 120s = 2mins
counter #(.M(M_Red)) countRed
(.clk(clk), .reset(reset), .state(1), .max_tick(max_tick_Red));
//Counter for amber light
//In traffic light sequence, change from green to amber after 12 clock cycles = 120s = 2mins
counter #(.M(M_Amber)) countAmber
(.clk(clk), .reset(reset), .state(1), .max_tick(max_tick_Amber));
endmodule
//Counter module:
//Counter - modulo M counter - counts 0 to M-1, then wraps around
module counter
//Parameters
//M = number of clock cycles the counter counts = max value
#(parameter M = 6)
//I/O signals
(
input wire clk, reset, state,
output wire max_tick
);
//Local parameter
//N = number of bits in counter
//N = ceiling(log2(M)) - definition at end of module
localparam N = clog2(M);
//Internal signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
//Body
//Rgister update
[email protected](posedge clk, posedge reset)
//Restart counter if reset is High or state is Low
//State = Low if this counter's light is not currently on
//State = High if this counter's light is currently on
if(reset)
r_reg <= 0;
//Only increment counter if state is High
//Only one of red, green, amber states is high
else if(state)
r_reg <= r_next;
else
r_reg <= 0;
//Next-state logic
assign r_next = (r_reg == M) ? 0: r_reg + 1;
//Output logic
//Max tick = HI when maximum count value is reached
//Max tick = LO otherwise
assign max_tick = (r_reg == M) ? 1'b1 : 1'b0;
//Ceiling log2() function definition
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
endmodule
非常感谢!我非常感谢你的帮助。你非常善良,并且很好地解释了解决方案。我已经通过用r_reg == M-1替换r_reg == M来解决问题,并且,通过对这个问题的这种新的理解,我希望不会再犯类似于这个问题的更多错误。谢谢! – user3051751 2015-04-02 10:25:54