VHDL：将std_logic_vector转换为整数时出错

我正在为vhdl（xilinx）编写代码，用于数字转速表。将std_logic_vector m1转换为整数时，编译器显示以下错误。VHDL：将std_logic_vector转换为整数时出错

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.numeric_std.all; 

entity tacho is 
    Port (A : in STD_LOGIC; 
      B : out STD_LOGIC_vector (15 downto 0)); 
end tacho; 

architecture Behavioral of tacho is 
component counter 
      port(
      clk: in std_logic; 
      m: out std_logic_vector (4 downto 0)); 
end component; 
signal m1 : std_logic_vector (4 downto 0); 
variable y: integer := 0; 
variable z: integer := 0;   
begin 
x: counter port map(A,m1); 
y:= to_integer(unsigned(m1)); --error1:Syntax error near ":=". error2:Expecting type void for <to_integer>. 
z:= y * 60; --Syntax error near ":=". 
B <= std_logic_vector(to_unsigned(z, 16)); 
end Behavioral;

我在很多网站上发现我写的语法是正确的。请帮忙！

来源

2017-03-27 Siddharth Jain

转速计通常计数一些采样间隔内的事件数量。这在你的设计中并不明显。 – user1155120

不要使用变量......至少：不是这样的。另外建议不要在合成中使用不受约束的整数，因为它们会扩展到32位值。 – JHBonarius

变量y和z不能在架构级别声明。使用信号代替，并且信号分配<=，如：

... 
    signal y : integer; 
    signal z: integer := 0;   
begin 
    x: counter port map(A, m1); 
    y <= to_integer(unsigned(m1)); 
    z <= y * 60; 
    B <= std_logic_vector(to_unsigned(z, 16)); 
...

或者干脆结合，并避免中间体y和z，如：

... 
    x: counter port map(A, m1); 
    B <= std_logic_vector(resize(60 * unsigned(m1), B'length)); 
    ...

来源

2017-03-27 18:05:34

非共享变量只能在被声明进程语句或子程序。你可以把你的缩放代码的过程：

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

entity tacho is 
    port (A: in std_logic; 
      B: out std_logic_vector (15 downto 0) 
    ); 
end entity tacho; 

architecture behavioral of tacho is 
    component counter is 
     port (
      clk: in std_logic; 
      m: out std_logic_vector (4 downto 0) 
     ); 
    end component; 
    signal m1 : std_logic_vector (4 downto 0); 
begin 

x: counter port map (A, m1); 

scaling: 
    process (m1) 
     variable y: integer := 0; 
     variable z: integer := 0; 
    begin 
     y := to_integer(unsigned(m1)); 
     z := y * 60; 
     B <= std_logic_vector(to_unsigned(z, 16)); 
    end process; 
end architecture behavioral;

或者你可以将你的计算，以一个子程序：

architecture scaled of tacho is 
    component counter is 
     port (
      clk: in std_logic; 
      m: out std_logic_vector (4 downto 0) 
     ); 
    end component; 
    signal m1 : std_logic_vector (4 downto 0); 
    function scale(m1: std_logic_vector (4 downto 0); SIZE: natural := 16) 
      return std_logic_vector is 
     variable y: integer; 
     variable z: integer; 
    begin 
     y := to_integer(unsigned(m1)); 
     z := y * 60; 
     return std_logic_vector(to_unsigned(z, SIZE)); 
    end function; 
begin 

x: counter port map (A, m1); 
scaled_output: 
    B <= scale(m1); 
end architecture;

这两种分析。

来源

2017-03-27 18:45:48 user1155120

VHDL：将std_logic_vector转换为整数时出错

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