有人可以帮助5x7点阵显示简单的VHDL代码用于charachter“R”吗？

Question

这是我正在使用的代码，但我需要减慢时钟以查看列和行如何变化。我认为我的计时存在一些问题：

library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
use IEEE.STD_LOGIC_ARITH.all; 
use IEEE.STD_LOGIC_UNSIGNED.all; 

-- Uncomment the following library declaration if using 
-- arithmetic functions with Signed or Unsigned values 
--use IEEE.NUMERIC_STD.ALL; 

-- Uncomment the following library declaration if instantiating 
-- any Xilinx primitives in this code. 
--library UNISIM; 
--use UNISIM.VComponents.all; 

entity dot_matrix is 

    port (main_clk, en : in std_logic; 


     switches : in std_logic_vector (3 downto 0); 
     rows  : inout std_logic_vector (6 downto 0); 
     col  : inout std_logic_vector (4 downto 0)); 

end dot_matrix; 

architecture Behavioral of dot_matrix is 

    signal row_count : std_logic_vector(2 downto 0); 
    signal counter : integer range 0 to 25000000 := 0; -- to divide the clock down 
    signal slow_clock : std_logic     := '0'; 

begin 

    clockdiv1 : process(main_clk) 
    begin 
    if main_clk'event and main_clk = '1' then 
     if counter = 24999999 then 
     counter <= 0; 
     slow_clock <= not slow_clock; 
     else 
     counter <= counter + 1; 
     end if; 
    end if; 
    end process clockdiv1; 

    SM : process (slow_clock) 
    begin 
    if (slow_clock'event and slow_clock = '1') then 
     if (en = '1') then 
     if (row_count = "100") then 
      row_count <= "000"; 
     else 
      row_count <= row_count + 1; 
     end if; 
     else 
     row_count <= "000"; 
     end if; 
    end if; 
    end process SM; 



    DIS : process (row_count) 
    begin 

    if row_count = "000" then   --1st clock count 
     col <= "01111";     --selecting 1st column 
     rows <= "1111111";    -- putting the data on the 1st column 

    elsif row_count = "001" then  -- 2nd clock count 
     col <= "10111";     -- selecting 2nd column 
     rows <= "1001000"; 

     row_count = "010" then   -- 3rd clock count 
     col <= "11011";    -- selecting 3rd column 
     rows <= "1001100"; 

     elsif row_count = "011" then  -- 4th clock count 
     col <= "11101";    -- selecting 4th column 
     rows <= "1001010"; 

     elsif row_count = "100" then  -- 5th clock count 
     col <= "11110";    -- selecting 5th column 
     rows <= "0110001"; 

     -- 1 1 1 1 0 

     -- 1 0 0 0 1 

     -- 1 0 0 0 1 

     -- 1 1 1 1 0 

     -- 1 0 1 0 0 

     -- 1 0 0 1 0 

     -- 1 0 0 0 1 

     end if; 
    end process DIS; 

end Behavioral; 

编辑：需要修复代码的缩进后添加一些文本。

Answer 1

存在丢失的“else if”语句在该行

row_count = "010" then 

也许这已经解决您的问题。

Answer 2

您正在使用您的慢时钟的初始值'0'。您需要验证您的合成器和目标技术是否支持此功能。有些FPGA可以，有些则不可以。或者，您可以添加复位信号并在启用复位时设置一个值。

其他评论：

• 作为youR.Fate说：你中途需要一个elsif在你的代码。
• 请勿使用IEEE.STD_LOGIC_ARITH和IEEE.STD_LOGIC_UNSIGNED。他们不是标准的。改用ieee.numeric_std。更多信息有关：http://www.sigasi.com/content/deprecated-ieee-libraries