1
所以我在设计一个verilog中的ALU,而我正在学习它。我想出了下面的代码: 测试平台:我的ALU在Verilog中的困难
module ALUtb;
reg clock = 1'b0;
reg [0:7] val1;
reg [0:7] val2;
initial begin
val1 = 8'b01010100;
val2 = 8'b10101000;
#50 $finish;
end
ALU piet(val1, val2,, clock);
always begin
#5 clock = ~clock
;
end
endmodule
Main code:
// Code your design here
module ALU(
a1, a2, out, clock
);
output [0:7] out;
input [0:7] a1;
input [0:7] a2;
input clock;
wire clock;
reg out;
wire co;
wire a1, a2;
wire [0:7] poep;
initial begin
$monitor("Out=%d, co=%d, a=%d, a2=%d, poep=%d, clock=%d", out, co, a1, a2, poep, clock);
end
always @ (posedge clock) begin
out <= poep;
end
adder addy(.output_byte(poep), .co(co), .a1(a1), .a2(a2), .clock(clock));
endmodule
module adder(
output_byte, co, a1, a2, clock
);
initial begin
output_byte = 8'b00000011;
end
input [0:7] a1;
input [0:7] a2;
input clock;
output [0:7] output_byte;
output output_bit;
output co;
wire c1;
reg b1, b2;
reg [0:7] output_byte;
wire output_bit;
integer i;
always @ (posedge clock) begin
for(i = 0; i < 8; i = i + 1) begin
b1 = (a1[i] & (1 << i));
b2 = (a2[i] & (1 << i));
#1 output_byte[i] = output_bit;
end
end
bitadder b_adder(.out(output_bit), .co(), .a1(b1), .a2(b2), .c1(c1));
endmodule
// Deze module is een 1-bits adder.
module bitadder(out, co, a1, a2, c1);
output out, co;
input a1, a2, c1;
wire out, co;
wire a1;
wire a2;
wire c1;
assign {co, out} = a1 + a2 + c1;
endmodule
所以我得到的输出:
Out= x, co=z, a= 84, a2=168, poep= 3, clock=0
Out= 3, co=z, a= 84, a2=168, poep= x, clock=1
Out= 3, co=z, a= 84, a2=168, poep= x, clock=0
Out= x, co=z, a= 84, a2=168, poep= x, clock=1
Out= x, co=z, a= 84, a2=168, poep= x, clock=0
Out= x, co=z, a= 84, a2=168, poep= x, clock=1
Out= x, co=z, a= 84, a2=168, poep= x, clock=0
Out= x, co=z, a= 84, a2=168, poep= x, clock=1
Out= x, co=z, a= 84, a2=168, poep= x, clock=0
Out= x, co=z, a= 84, a2=168, poep= x, clock=1
Out= x, co=z, a= 84, a2=168, poep= x, clock=0
正如你可以看到这只是一个8位加法器。因为即使这样也行不通,我们还没有进行。 我的具体问题是:为什么输出不正常变化? Poep就像是实际输出的缓冲区。 co是进位位,a是第一个数字,a2是第二个数字,c1是进位位,其余的应该说明它自己。 为什么我的输出未定义?
任何帮助将不胜感激!
在此先感谢!
'#1 output_byte [i] = output_bit;'不可合成。你甚至不需要'adder'中的'always'块,你需要连接8个'bitadder' – Greg